Marvell’s ThunderX3 Server Team Loses VP/GM and Lead Architect

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One of the key drivers in the Arm server space over the last few years has been the cohesion of the different product teams attempting to build the next processor to attack the dominance of x86 in the enterprise market. A number of companies and products have come and gone (Qualcomm’s Centriq) or been acquired (Annapurna by Amazon, Applied Micro by Ampere), with varying degrees of success, some of which is linked to the key personnel in each team. One of our readers has recently highlighted us to a recent movement in this space: Gopal Hegde, the VP/GM of the ThunderX Processor Business Unit at Marvell, has now left the company.

ThunderX was originally under the banner of Cavium, and the company released two generations of products built on Arm: ThunderX, and ThunderX2. We reviewed both systems, with ThunderX in 2016 and ThunderX2 in 2018, the latter being noted as a potential competitor in defined workloads as well as cloud and hosting providers, given the right price. We’ve seen ThunderX2 have some success in container deployments, as well as HPC. However, during the deployment of ThunderX2, Cavium was acquired by Marvell for $5.5 billion USD, with the company looking to bolster its CPU, networking, and security assets. That acquisition was completed in July 2018.

It was noted that before the acquisition, Cavium was keen to highlight it had a regular roadmap planned for its ThunderX line of processors and servers. ThunderX3 was understood to be an aggressive design suited for a wide range of markets. However, after the acquisition, limited information was provided beyond what was said by Cavium. It was with some personal frustration that attempting to discuss anything about ThunderX3 at the Marvell booth at Supercomputing 2019 was met with a wall of silence. It is typically very odd for a company to stay silent for so long, especially on a product where details had been expected a few months prior, based on previous release cycles. Conversing with peers at the time, we came to the same realization that ThunderX3 was, perhaps, later than expected.

However, much to our surprise, Marvell reached out to us in March this year to discuss the initial steps of ThunderX3. While it wasn’t a deep dive into the architecture, we were certainly very glad to be told the highlights – a 3rd generation custom microarchitecture on top of Arm v8.3+, using four threads per core, scaling up to 96 cores or 384 threads per chip. This was combined with 8x DDR4-3200 memory controllers, 64 lanes of PCIe 4.0, and four 128-bit SIMD units per core. This is all to be built on TSMC 7nm. In our briefing, we were told that a critical element to the design of the chip is that it remains monolithic, and that the chip is to target a significant number of cloud-based workloads and HPC workloads with its differentiation (such as SMT4) to allow for higher utilization of the underlying hardware. We are expecting more information about ThunderX3 at Hot Chips in August, as well as an update on the roadmap.

Heading up Cavium and Marvell’s efforts for the ThunderX project was Gopal Hegde. Gopal cites his experience in helping build the engineering teams across several sites worldwide, and as a core and platform engineer, helped define the specifications, the silicon, the brand, and the roadmap as part of a wider team. This was a position held by Gopal since 2014, and before that he was COO of Calxeda, according to his LinkedIn. 


Gopal Hegde, Image from LinkedIn

It is worth noting that Dr. Shubu Mukherjee, Lead Architect for ThunderX and ThunderX2, also left the company in December 2019, to work at SiFive. Gopal Hegde has since transitioned to SVP of Engineering and Operations at SiMa.ai, a startup looking to provide energy efficient machine learning edge compute. 

Having two key personnel losses in short succession inevitably put up a few question marks. A few of my industry key leads pointed to Gopal moving position as perhaps an inflection point in Marvell’s ThunderX project strategy. At this point we’re aware that while ThunderX2 has been generating revenue, we’re unsure if it has actually provided a positive return at all, let alone sufficient revenue for Marvell since the acquisition to justify the purchase. Development of ThunderX3, a large chip on a leading process node, is going to take a fair amount of investment from Marvell in order to execute both on time and at scale. Usually when we consider the development of new chips by a startup, we talk about the ‘cash burn’ of the company as a way of measuring how much money it is going through until a product is launched. We rarely talk about it for the bigger names, the Intels, the Qualcomms, or the Marvells, but it might be poignant here. Marvell doesn’t make these numbers public for obvious reasons.

The loss of two big names might give cause for Marvell to reconsider the feasibility of the project in its entirety. Qualcomm famously put the lid on its Centriq server project as a way of removing parts of the company that weren’t generating sufficient revenue, and the start of that process publically began with the announcement of the senior VP of the business unit leaving the company. With that being said, Marvell’s ThunderX3 is still on the list of presentations at Hot Chips in August and the company still seems positively bouyant about the ThunderX3 release.

We reached out to Marvell for commentary about the move and the future of the ThunderX processor family, and spoke to Raghib Hussain, Marvell Chief Strategy Officer and EVP of the Networking and Processors Group, and Raj Singh. Raghib is a co-founder of Cavium, and took on a senior role at Marvell after the acquisition. Raghib’s background has primarily involved engineering roles. 

 “We made the strategic decision to integrate the marketing and engineering teams for all of our processor businesses, including OCTEON and ThunderX, under Raj Singh [back in September 2019]. Looking at the data infrastructure market moving forward, we see more similarities and synergies between our compute-focused segments. Under Raj’s leadership, this organization now represents the world’s largest and most scalable Arm-based infrastructure processor business, with solutions scaling from a few cores all the way up to server-class. Marvell’s Arm processor portfolio is unsurpassed for the data infrastructure market and is bringing optimized power, performance and TCO advantages to applications from enterprise appliances to 5G base stations, servers in the data center, and in the near future – new and emerging edge data center applications.”

Raj Singh is also an ex-Cavium employee, who has servers as part of his mandate as Marvell’s EVP of the Processor Business Group under Raghib Hussain since September 2019. 

Marvell also gave us the opportunity to ask questions on the business as well as the structure of where ThunderX fits in. We were told that the ThunderX project fits under the banner of ‘strategic bets’, and by grouping the processor line under the same banner as other products such as automtive ethernet and investments in the datacenter, Marvell aims to offer a datacentric solution to its customers and is in it for the long haul. At this point in time, immediate return isn’t so much the main metric of the project, but the potential for a return down the road, which if a chip design is run more like a startup, might not be a feasible strategy if revenue has to start coming in immediately.

Compared to other companies in this space, Marvell explained that it has the ability to build IP that can be used across a dozen products in its portfolio, such as a memory controller that might appear across Octeon, ThunderX, Avera FPGAs, and this allows it to amortize the cost of research and development across many projects from the mature businesses, the growth businesses, and the strategic bets. Marvell points to its growing R&D spend as a function of revenue, citing it as one of the highest percentages in the fabless semiconductor space.

The next big announcement for ThunderX3 is at Hot Chips in August. Marvell seem very keen to engage with us for a microarchitecture disclosure, so stay tuned for that.

Source: SiMa.ai Press Release

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