Western Digital and Kioxia Announce BiCS5 112-Layer 3D NAND

Western Digital and Kioxia have announced the successful development of their newest generation of 3D NAND flash memory. Their fifth-generation BiCS 3D NAND has commenced production in the form of a 512 Gbit TLC part, but will not ramp up to “meaningful commercial volumes” until the second half of the year. Other parts planned for this generation include 1Tbit TLC and 1.33 Tbit QLC dies.

The BiCS5 design uses 112 layers compared to 96 for BiCS4. BiCS5 is the second generation from WDC/Kioxia to be constructed with string stacking, and is probably built as two stacks of about 56 active layers each. Even though 112 layers is only a ~16% increase over the previous generation, the companies are claiming a density increase of up to 40% (comparing 112L 512Gb TLC against 96L 256Gb TLC, by bits per wafer), thanks to other tweaks to the design that allow for shrinking horizontal dimensions. The density of the memory array itself is said to be about 20% higher. The memory interface speed has been increased by 50%, which should put it at 1.2GT/s, on par with most of the 96L competitors.

BiCS5 parts will begin sampling this quarter. With production ramping up in the second half of the year, SSDs and other products using BICS5 will likely hit the market around the end of 2020 at the earliest. Western Digital has previously stated that they intended for the BiCS5 transition to require lower CapEx than the 64L to 96L transition, reversing the trend of steadily more expensive generational updates. This means that the migration to 112L will probably be even slower than the last transition, and 96L BiCS4 will be a major part of their production volume for quite a while.

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