TSMC Responds to Lawsuit by GlobalFoundries: Allegations Are Baseless
TSMC has responded to GlobalFoundries accusations of patents infringements. The world’s largest foundry said that it would defend itself in courts and that it considered allegations as baseless. The contract maker of semiconductors said that throughout its history it was granted 37,000 patents and naturally considers itself one of the leaders in the industry.
On Monday GlobalFoundries said that TSMC, a number of its customers, as well as makers of various products infringed 16 of its patents covering various aspects of chip manufacturing. In particular, GlobalFoundries claims that TSMC’s 7 nm, 10 nm, 12 nm, 16 nm, and 28 nm nodes illegally use its intellectual property. Among defendants, the company named Apple, Broadcom, Mediatek, NVIDIA, Qualcomm, Xilinx and many others. GlobalFoundries seeks damages from TSMC and wants courts to ban shipments of products that use infringing semiconductors into the USA and Germany.
|GlobalFoundries vs. TSMC et al|
|Fabless Chip Designers||Consumer Product Manufacturers||Electronic Component Distributors|
Quite naturally, TSMC denies any allegations and claims that it will defend itself in courts. The company stresses that it spends billions of dollars on R&D and has been granted 37,000 patents worldwide. Typically, high-tech companies counter-sue each other in patent infringement cases, so it will not be surprising if TSMC decides to sue GlobalFoundries. In the end, this is what patents are for. Meanwhile, unlike GlobalFoundries, TSMC will unlikely sue fabless designers of semiconductors that use the former’s services to a large degree because the vast majority of chip developers are it slients.
The statement by TSMC reads as follows:
TSMC is in the process of reviewing the complaints filed by GlobalFoundries on August 26, but is confident that GlobalFoundries’ allegations are baseless. As a leading innovator, TSMC invests billions of dollars each year to independently develop its world-class, leading-edge semiconductor manufacturing technologies. As a result, TSMC has established one of the largest semiconductor portfolios with more than 37,000 patents worldwide and a top 10 ranking for US patent grants for 3 consecutive years since 2016. We are disappointed to see a foundry peer resort to meritless lawsuits instead of competing in the marketplace with technology. TSMC is proud of its technology leadership, manufacturing excellence, and unwavering commitment to customers. We will fight vigorously, using any and all options, to protect our proprietary technologies.
|GlobalFoundries vs. TSMC et al, GF’s Patents in the Cases|
|Bit Cell With Double Patterned Metal Layer Structures||US 8,823,178||Juhan Kim, Mahbub Rashed|
|Semiconductor device with transistor local interconnects||US 8,581,348||Mahbub Rashed, Steven Soss, Jongwook Kye, Irene Y. Lin, James Benjamin Gullette, Chinh Nguyen, Jeff Kim, Marc Tarabbia, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Scott Johnson, Subramani KengeriSuresh Venkatesan|
|Semiconductor device with transistor local interconnects||US 9,355,910||Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan|
|Introduction of metal impurity to change workfunction of conductive electrodes||US 7,425,497||Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri, Yun Y. Wang,Keith Kwong Hon Wong|
|Semiconductor device having contact layer providing electrical connections||US 8,598,633||Marc Tarabbia, James B. Gullette, Mahbub RashedDavid S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng MaYunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan|
|Method of forming a metal or metal nitride interface layer between silicon nitride and copper||US 6,518,167||Lu You, Matthew S. Buynoski, Paul R. Besser, Jeremias D. Romero, Pin-Chin, Connie Wang, Minh Q. Tran|
|Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects||US 8,039,966||Chih-Chao Yang, Chao-Kun Hu|
|Introduction of metal impurity to change workfunction of conductive electrodes||US 7,750,418||Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri, Yun Y. Wang, Keith Kwong Hon Wong|
|Methods of forming FinFET devices with a shared gate structure||US 8,936,986||Andy C. Wei, Dae Geun Yang|
|Semiconductor device with stressed fin sections||US 8,912,603||Scott Luning, Frank Scott Johnson|
|Multiple dielectric FinFET structure and method||US 7,378,357||William F. Clark, Jr., Edward J. Nowak|
|Bit cell with double patterned metal layer structures||US 9,105,643||Juhan Kim, Mahbub Rashed|
|Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor||US 9,082,877||Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, and Xiaojun Yu|
|Hybrid contact structure with low aspect ratio contacts in a semiconductor device||DE 102011002769||Kai Frohberg, Ralf Richter|
|Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas||DE 102011004320||Gunda Beernink, Markus Lenski|
|Semiconductor device with transistor local interconnects||DE 102012219375||Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan|