TSMC & Broadcom Develop 1,700 mm2 CoWoS Interposer: 2X Larger Than Reticles

TSMC & Broadcom Develop 1,700 mm2 CoWoS Interposer: 2X Larger Than Reticles 1

With transistor shrinks slowing and demand for HPC gear growing, as of late there has been an increased interest in chip solutions larger than the reticle size of a lithography machine – that is, chips bigger than the maximum size that a single chip can be produced. We’ve already seen efforts such as Cerebras’ truly massive 1.2 trillion transistor wafer scale engine, and they aren’t alone. As it turns out, TSMC and Broadcom have also been playing with the idea of oversized chips, and this week they’ve announced their plans to develop a supersized interposer to be used in Chip-on-Wafer-on-Substrate (CoWoS) packaging.

Overall, the proposed 1,700 mm² interposer is twice the size of TSMC’s 858 mm² reticle limit. Of course, TSMC can’t actually produce a single interposer this large all in one shot – that’s what the reticle limit is all about – so instead the company is essentially stitching together multiple interposers, building them next to each other on a single wafer and then connecting them. The net result is that an oversized interposer can be made to function without violating reticle limits.

The new CoWoS platform will initially be used for a new processor from Broadcom for the HPC market, and will be made using TSMC’s EUV-based 5 nm (N5) process technology. This system-in-package product features ‘multiple’ SoC dies as well as six HBM2 stacks with a total capacity of 96 GB. According to Broadcom’s press release, the chip will have a total bandwidth of up to 2.7 TB/s, which is in line with what Samsung’s latest HBM2E chips can offer.

By doubling the size of SiPs using its mask stitching technology, TSMC and its partners can throw in a significantly higher number of transistors at compute-intensive workloads. This is particularly important for HPC and AI applications that are developing very fast these days. It is noteworthy that TSMC will continue refining its CoWoS technology, so expect SIPs larger than 1,700 mm2 going forward.

Greg Dix, vice president of engineering for the ASIC products division at Broadcom, said the following:

“Broadcom is happy to have collaborated with TSMC on advancing the CoWoS platform to address a host of design challenges at 7nm and beyond. Together, we are driving innovation with unprecedented compute, I/O and memory integration and paving the way for new and emerging applications including AI, Machine Learning, and 5G Networking.”

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Source: TSMC

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