Rambus Develops HBM2E Controller & PHY: 3.2 Gbps, 1024-Bit Bus

The latest enhancements to the HBM2 standard will clearly be appreciated by developers of memory bandwidth-hungry ASICs, however in order to add support of HBM2E to their designs, they are also going to need an appropriate controller as well as physical interface. For many companies developing of such IP in-house does not make financial sense, so Rambus has designed a highly-integrated HBM2E solution for licensing.

The HBM2E standard supports 12-Hi DRAM stacks as well as memory devices of up to 16 Gbps, thus enabling to build up to 24 GB stacks using a 1024-bit bus. At the same time, the new specification officially supports data rates of up to 3.2 Gbps, which results in 409.6 GB/s bandwidth per stack. Rambus’s HBM2E solution includes a controller that can work with 12-Hi KGSDs (known good stack dies) as well as a verified 1024-bit PHY that supports speeds of up to 3.2 Gbps. 

Rambus Develops HBM2E Controller & PHY: 3.2 Gbps, 1024-Bit Bus 1

The Rambus HBM2E controller core (originally developed by Northwest Logic) is DFI 3.1 compatible (with appropriate extensions) and supports AXI, OCP or proprietary interfaces to connect to integrator logic. Meanwhile, the controller also supports Look-Ahead command processing (a standard way to trim latencies) as well as channel densities of up to 24 Gb.

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Licensees of Rambus’s HBM2E solution will get everything they need to integrate it into their designs, including source code of the controller (in a bid to synthesize it for a particular process technology) as well as fully-characterized hard macros (GDSII) of the interface. Alternatively, engineers from Rambus can help integrate the HBM2E IP support for a fee.

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Source: Rambus

Rambus Develops HBM2E Controller & PHY: 3.2 Gbps, 1024-Bit Bus 2
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