Big quote: “Hello, world! I am RV16X-NANO, made from CNTs,” reads the first message from the first program to run on a carbon nanotube (CNT) processor. Built by MIT physicists, Nano is eighty times larger than its predecessor at 14,702 carbon nanotube field-effect transistors (CNFETs), and it’s capable of running the 32-bit RISC-V instruction set on 16-bit data. The thing most remarkable about Nano, however, is not what’s new about it, but what’s old.
Truthfully, it has been some time since Moore’s law, the propensity for processors to double in transistor count every two years, has been entirely accurate. The fundamental properties of silicon are beginning to limit development and will significantly curtail future performance gains, yet with 50 years and billions invested, it seems preposterous that any ‘beyond-silicon’ technology could power the computers of tomorrow. And yet, Nano might do just that, by harnessing its ability to be designed and built like a regular silicon wafer, while using carbon to net theoretical triple performance at one-third the power.
Nano began life much like all processors, a 150mm wafer with a pattern carved out of it by a regular chip fab. Dipped into a solution of carbon nanotubes bound together like microscopic spaghetti, it re-emerged with its semi-conductive carbon nanotubes stuck in the pattern of transistors and logic gates already etched on it. It then undergoes a process called ‘RINSE,’ removal of incubated nanotubes through selective exfoliation, by being coated with a polymer then dipped in a solvent. This has the effect of reducing the CNT layer to being just one tube, removing the large clumps of CNTs that stick together over 250 times more effectively than previous methods.
One of the challenges facing CNT processors has been difficulty in separating N-type and P-type transistors, which are “on” for 1 bit and “off” for 0 bit and the reverse, respectively. The difference is important for binary computing, and to perfect it, the researchers introduced ‘MIXED,’ metal interface engineering crossed with electrostatic doping. Occurring after RINSE, small platinum or titanium components are added to each transistor, then the wafer is coated in an oxide which acts as a sealant, improving performance. After that, Nano was just about done.
Part of Nano’s brilliance is its ability to overcome the intrinsic flaws of manufacturing CNTs, which had been a roadblock to researchers previously. A very small portion of CNTs have a high concentration of conductive metal impurities that force the transistor to be always on or always off, which has a cascading effect that can cripple the whole processor. The theoretical purity required to prevent this is 99.999999%; clearly unachievable; and thus the researchers invented ‘DREAM,’ designing resiliency against metallic CNT.
Researchers observed that though one impure CNT might ruin one logic gate, if employed in a certain way in another, it can be harmless. They crafted software to predict when impure CNTs would cause the least damage, and they designed Nano with this resilient architecture. “The ‘DREAM’ pun is very much intended, because it’s the dream solution,” says Max Shulaker, co-author. “This allows us to buy carbon nanotubes off the shelf [with 99.99% purity], drop them onto a wafer, and just build our circuit like normal, without doing anything else special.”
As Nano had its wafer constructed by equipment normally used for regular silicon processors, runs the open-source RISC-V instruction set, and was designed using publicly available Bluespec software, there appears to be little preventing it from being scaled up. DARPA, who supported the research, have already begun to implement Nano’s manufacturing techniques at an experimental fab. “We think it’s no longer a question of if, but when,” Shulaker said, adding that CNT products could appear on shelves in as few as five years.
Image Credit: Laura Ockel on Unsplash
Modern microprocessor built from complementary carbon nanotube transistors, Nature (August 2019)